1. Field of the Invention
The present invention relates to a method for forming a fuse in a semiconductor device, and more particularly to a method for forming a fuse in a semiconductor device, which can prevent corrosion produced during a formation of the fuse in metal wiring, by using patterns obtained through a damascene process.
2. Description of the Prior Art
As generally known in the art, aluminium (Al), which is used as a material for metal wiring, has a specific resistance of 2.7 μΩcm, which is the fourth lowest specific resistance of all existing metals, and a good electric conductivity, resulting in its application in the production of semiconductor devices. However, aluminium is known to be poor in resistance against an electro-migration (EM), which produces voids and hillocks originating from mass transport.
Copper (Cu) has become a substitute material for wiring materials in the next generation, as it has a specific resistance of 1.7 μΩcm and a good resistance against electro-migration, as compared with aluminium.
The dual damascene pattern production method that defines a contact hole and a wiring region, as employed generally, utilizing copper as a wiring material.
The dual damascene pattern production process includes the step sequences of carrying out lithography, etching and striping, trench lithography, trench etching and striping or trench lithography, trench etching and striping, lithography, etching and striping.
FIGS. 1A and 1B are sectional views illustrating each step of a conventional method for forming a fuse in a semiconductor device.
Referring to FIG. 1A, the left drawing is a layout 2 for forming metal wiring in a fuse box, and the right drawing is a sectional view taken along line A-B in the left drawing showing the metal wiring in the fuse box fabricated by using the left drawing as a mask.
To explain specifically, a metal wiring process is carried out in the lower part of the device and then an insulating layer 1 is sprayed on the metal wiring, and a trench for metal wiring is formed using a mask drawn like the fuse layout 2 for the metal wiring.
Further, a metal wiring barrier layer 3 is sprayed on the trench, and metal wiring materials are sprayed thickly and performing a chemical-mechanical polishing (CMP) process to result in the formation of metal wiring 4 in the region that will be used for a fuse.
Referring to FIG. 1B, the left drawing is a layout 6 of the fuse box shown in FIG. 1A, and the right drawing is a sectional view taken along line A-B showing the fuse box with an opening fabricated by using the left drawing of FIG. 1B as a mask.
To explain specifically, a passivation layer 5 is sprayed on the resultant structure including the metal wiring and the insulating layer 1, and then etching of the passivation layer 5 and the metal wiring 4 is performed using a drawn mask like the layout 6 of the fuse open box to expose the metal wiring barrier layer 3 that will be used as a fuse.
However, regarding the conventional method for forming a fuse in a semiconductor device, when using copper as the metal wiring, there is a probability that copper is corroded while being etched, exposing the fuse box. Further, it is difficult to perform etching of an oxide layer and copper at the same time. In practice, it has been considerably difficult to leave just the metal wiring barrier layer that would be used as a fuse layer.
Further, the corrosion of copper originating from the exposure of the fuse reduces the reliability of the semiconductor device considerably, and as there is no oxide layer left on the metal wiring barrier layer, it is considerably difficult to cut the fuse with a laser cutting method, which is a general cutting method employed to cut the fuse. This is because when the laser cutting is performed, it is known that it is necessary to leave an oxide layer of a certain thickness on the layer that will be used as a fuse.